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rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8361 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 world wide web site: http://www.analog.com fax: 781/326-8703 ? analog devices, inc., 2001 lf to 2.5 ghz trupwr detector functional block diagrams micro_soic rfin iref pwdn vpos fltr sref vrms comm band-gap reference error amp 2 2 AD8361 internal filter add offset trans- conductance cells i i 7.5 buffer sot-23-6l rfin pwdn vpos fltr vrms comm band-gap reference 2 2 AD8361 internal filter trans- conductance cells i i error amp 7.5 buffer features calibrated rms response excellent temperature stability up to 30 db input range at 2.5 ghz 700 mv rms, 10 dbm re 50 maximum input 0.25 db linear response up to 2.5 ghz single supply operation: 2.7 v to 5.5 v low power: 3.3 mw at 3 v supply rapid power-down to less than 1 a applications measurement of cdma, w-cdma, qam, other complex modulation waveforms rf transmitter or receiver power measurement product description the AD8361 is a mean-responding power detector for use in high- frequency receiver and transmitter signal chains, up to 2.5 ghz. it is very easy to apply. it requires only a single s upply between 2.7 v and 5.5 v, power supply decoupling capacitor and an input coupling capacitor in most applications. the output is a linear-responding dc voltage with a conversion gain of 7.5 v/v rms. an external ?ter capacitor can be added to in crease the ave rag- ing time constant. rfin ?v rms 3.0 1.6 0 0.5 0.1 0.2 0.3 0.4 2.6 2.2 2.0 1.8 2.8 2.4 v rms ?volts 1.4 1.2 1.0 0.6 0.8 0.4 0.2 0.0 supply reference mode internal reference mode ground reference mode figure 1. output in the three reference modes, supply 3 v, frequency 1.9 ghz (sot-23-6l package ground reference mode only) trupwr is a trademark of analog devices, inc. the AD8361 is intended for true power measurement of simple and complex waveforms. the device is particularly useful for measuring high crest-factor ( high peak-to-rms ratio) signals, such as cdma and w-cdma. the AD8361 has three operating modes to accommodate a variety of analog-to-digital converter requirements: 1. ground referenced mode, in which the origin is zero; 2. internal reference mode, which offsets the output 350 mv above ground; 3. supply reference mode, w hich offsets the output to v s /7.5. the AD8361 is speci?d for operation from ?0 c to +85 c and is available in 8-lead micro_soic and 6-lead sot packages. it is fabricated on a proprietary high f t silicon bipolar process.
C2C rev. b AD8361?pecifications (t a = 25 c, v s = 3 v, f rf = 900 mhz, ground reference output mode, unless otherwise noted.) parameter condition min typ max unit signal input interface (input rfin) frequency range 1 2.5 ghz linear response upper limit v s = 3 v 390 mv rms equivalent dbm re 50 ? 4.9 dbm v s = 5 v 660 mv rms equivalent dbm re 50 ? 9.4 dbm input impedance 2 225 1 ? pf rms conversion (input rfin to output v rms) conversion gain 7.5 v/v rms f rf = 100 mhz, v s = 5 v 6.5 8.5 v/v rms dynamic range error referred to best fit line 3 0.25 db error 4 cw input, ?0 c < t a < +85 c14db 1 db error cw input, ?0 c < t a < +85 c23db 2 db error cw input, ?0 c < t a < +85 c26db cw input, v s = 5 v, ?0 c < t a < +85 c30db intercept-induced dynamic internal reference mode 1 db range reduction 5, 6 supply reference mode, v s = 3.0 v 1 db supply reference mode, v s = 5.0 v 1.5 db deviation from cw response 5.5 db peak-to-average ratio (is95 reverse link) 0.2 db 12 db peak-to-average ratio (w-cdma 4 channels) 1.0 db 18 db peak-to-average ratio (w-cdma 15 channels) 1.2 db output intercept 5 inferred from best fit line 3 ground reference mode (grm) 0 v at sref, v s at iref 0 v f rf = 100 mhz, v s = 5 v ?0 +150 mv internal reference mode (irm) 0 v at sref, iref open 350 mv f rf = 100 mhz, v s = 5 v 300 500 mv supply reference mode (srm) 0 v at iref, 3 v at sref 400 mv f rf = 100 mhz, v s = 5 v 590 750 mv 0 v at iref, v s at sref v s /7.5 v power-down interface pwdn hi threshold 2.7 v s 5.5 v, ?0 c < t a < +85 cv s 0.5 v pwdn lo threshold 2.7 v s 5.5 v, ?0 c < t a < +85 c0.1v power-up response time 2 pf at fltr pin, 224 mv rms at rfin 5 s 100 nf at fltr pin, 224 mv rms at rfin 320 s pwdn bias current <1 a power supplies operating range ?0 c < t a < +85 c2.75.5v quiescent current 0 mv rms at rfin, pwdn input lo 7 1.1 ma power-down current grm or irm, 0 mv rms at rfin, pwdn input hi <1 a srm, 0 mv rms at rfin, pwdn input hi 10 v s a notes 1 operation at arbitrarily low frequencies is possible; see applications section. 2 tpc 12 and figure 10 show impedance versus frequency for the micro_soic and sot respectively. 3 calculated using linear regression. 4 compensated for output reference temperature drift; see applications section. 5 sot-23-6l operates in ground reference mode only. 6 the available output swing, and hence the dynamic range, is altered by both supply voltage and reference mode; see figures 5 an d 6. 7 supply current is input level dependant; see tpc 11. speci?ations subject to change without notice.
AD8361 rev. b C3C absolute maximum ratings 1 supply voltage v s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v sref, pwdn . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 v, v s iref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v s ?0.3 v, v s rfin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 v rms equivalent power re 50 ? . . . . . . . . . . . . . . . . . . . 13 dbm internal power dissipation 2 . . . . . . . . . . . . . . . . . . . . 200 mw sot-23-6l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 mw micro_soic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 mw maximum junction temperature . . . . . . . . . . . . . . . . . 125 c operating temperature range . . . . . . . . . . ?0 c to +85 c storage temperature range . . . . . . . . . . . ?5 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 specification is for the device in free air. sot-23-6l: ja = 230 c/w; jc = 92 c/w. micro_soic: ja = 200 c/w; jc = 44 c/w. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8361 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. pin function descriptions pin micro sot name description 1 6 vpos supply voltage pin. operational range 2.7 v to 5.5 v. 2 iref output reference control pin. inter- nal reference mode enabled when pin is left open. otherwise, this pin should be tied to vpos. do not ground this pin. 3 5 rfin signal input pin. must be driven from an ac-coupled source. the low frequency real input impedance is 225 ? . 4 4 pwdn power-down pin. for the device to operate as a detector it needs a logical low input (less than 100 mv). when a logic high (greater t han v s 0.5 v) is applied, the device is turned off and the supply current goes to nearly zero (ground and internal reference mode less than 1 a, supply reference mode v s divided by 100 k ? ). 5 2 comm device ground pin. 6 3 fltr by placing a capacitor between this pin and vpos, the corner frequency of the modulation ?ter is lowered. the on- chip ?ter is formed with 27 pf 2 k ? for small input signals. 7 1 vrms output pin. near-rail-to-rail voltage output with limited current drive capa- bilities. expected load >10 k ? to ground. 8 sref s upply reference control pin. to enable supply reference mode this pin must be connected to vpos, other- wise it should be connected to comm (ground). pin configurations micro_soic AD8361 vpos iref rfin pwdn sref vrms fltr comm 1 2 3 4 5 6 7 8 sot-23-6l 1 2 3 4 6 5 AD8361 vrms rfin pwdn vpos fltr comm ordering guide model temperature range package description package option AD8361arm * ?0 c to +85 c tube, 8-lead micro_soic rm-8 AD8361arm-reel 13" tape and reel AD8361arm-reel7 7" tape and reel AD8361art-reel 13" tape and reel rt-6 AD8361art-reel7 7" tape and reel AD8361-eval evaluation board micro_soic AD8361art-eval evaluation board sot-23-6l * device branded as j3a. warning! esd sensitive device
AD8361 C4C rev. b typical performance characteristics input v rms 2.8 2.6 0.8 0 0.5 0.1 0.2 0.3 0.4 2.0 1.4 1.2 1.0 2.4 2.2 1.6 1.8 output volts 0.6 0.4 0.2 0.0 900mhz 100mhz 1900mhz 2.5ghz tpc 1. output vs. input level, frequencies 100 mhz, 900 mhz, 1900 mhz, and 2500 mhz, supply 2.7 v, ground reference mode, micro_soic input v rms 5.5 1.5 0 0.5 0.1 0.2 0.3 0.4 4.0 3.0 2.5 2.0 5.0 4.5 3.5 output volts 1.0 0.5 0.0 5.5v 5.0v 3.0v 2.7v 0.6 0.7 0.8 tpc 2. output vs. input level, supply 2.7 v, 3.0 v, 5.0 v, and 5.5 v, frequency 900 mhz input v rms 5.0 1.5 0 0.5 0.1 0.2 0.3 0.4 4.0 3.0 2.5 2.0 4.5 3.5 output volts 1.0 0.5 0.0 0.6 0.7 0.8 cw is95 reverse link wcdma 4- and 15-channel tpc 3. output vs. input level with different waveforms sine wave (cw), is95 reverse link, w-cdma 4-channel and w-cdma 15-channel, supply 5.0 v input v rms 3.0 2.5 1.0 0.4 (+5dbm) 0.01 1.5 0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.1 ( 7dbm) 0.02 ( 21dbm) mean 3 sigma tpc 4. error from linear reference vs. input level, 3 sigma to either side of mean, sine wave, supply 3.0 v, frequency 900 mhz input v rms 3.0 2.5 1.0 0.6 (+8.6dbm) 0.01 1.5 0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.1 ( 7dbm) 0.02 ( 21dbm) mean 3 sigma tpc 5. error from linear reference vs. input level, 3 sigma to either side of mean, sine-wave, supply 5.0 v, frequency 900 mhz input v rms 3.0 2.5 1.0 1.0 0.01 0.1 1.5 0.0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.02 0.6 0.2 is95 reverse link cw 15-channel 4-channel tpc 6. error from cw linear reference vs. input with different waveforms sine wave (cw), is95 reverse link, w-cdma 4-channel and w-cdma 15-channel, supply 3.0 v, frequency 900 mhz
AD8361 rev. b C5C input v rms 3.0 2.5 1.0 0.4 (+5dbm) 0.01 1.5 0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.1 ( 7dbm) 0.02 ( 21dbm) mean 3 sigma tpc 7. error from cw linear reference vs. input, 3 sigma to either side of mean, is95 reverse link signal, supply 3.0 v, frequency 900 mhz input v rms 3.0 2.5 1.0 0.6 (+8.6dbm) 0.01 1.5 0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.1 ( 7dbm) 0.02 ( 21dbm) mean 3 sigma tpc 8. error from cw linear reference vs. input level, 3 sigma to either side of mean, is95 reverse link signal, supply 5.0 v, frequency 900 mhz input v rms 3.0 2.5 1.0 0.4 (+5dbm) 0.01 1.5 0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.1 ( 7dbm) 0.02 ( 21dbm) 40 c +85 c tpc 9. output delta from +25 c vs. input level, 3 sigma to either side of mean sine wave, supply 3.0 v, frequency 900 mhz, temperature C40 c to +85 c input v rms 3.0 2.5 1.0 0.4 (+5dbm) 0.01 1.5 0 0.5 2.0 0.5 1.0 error db 1.5 2.0 2.5 3.0 0.1 ( 7dbm) 0.02 ( 21dbm) 40 c +85 c tpc 10. output delta from +25 c vs. input level, 3 sigma to either side of mean sine wave, supply 3.0 v, frequency 1900 mhz, temperature C40 c to +85 c input v rms 11 3 0 0.5 0.1 0.2 0.3 0.4 8 6 5 4 10 9 7 supply current ma 2 1 0 0.6 0.7 0.8 +85 c 40 c +25 c v s = 5v input out of range +25 c +85 c 40 c v s = 3v input out of range tpc 11. supply current vs. input level, supplies 3.0 v, and 5.0 v, temperatures C40 c, +25 c, and +85 c frequency mhz 0 500 1000 250 200 150 shunt resistance 100 50 0 2000 2500 1.4 1.2 1.0 shunt capacitance pf 0.8 0.6 0.4 1500 +85 c +25 c 40 c +85 c +25 c 40 c 1.6 1.8 tpc 12. input imp edance vs. frequency, supply 3 v, temperatures C40 c, +25 c, and +85 c, micro_soic (see applications for sot-23-6l data)
AD8361 C6C rev. b temperature c 0.02 40 40 20 0 20 0.03 0.01 0.00 0.01 0.02 intercept change volts 0.03 0.04 0.05 60 80 100 mean 3 sigma tpc 13. output reference change vs. temperature, supply 3 v, ground reference mode temperature c 0.01 40 40 20 0 20 0.02 0.01 0.00 intercept change volts 0.02 0.03 60 80 100 mean 3 sigma tpc 14. output reference change vs. temperature, supply 3 v, internal reference mode (micro_soic only) temperature c 0.02 40 40 20 0 20 0.03 0.01 0.00 0.01 0.02 intercept change volts 0.03 0.04 0.05 60 80 100 mean 3 sigma tpc 15. output reference change vs. temperature, supply 3 v, supply reference mode (micro_soic only) temperature c 0.02 40 40 20 0 20 0.12 0.08 0.06 0.04 0.10 gain change v/v rms 0.00 0.02 0.04 60 80 100 mean 3 sigma 0.06 0.14 0.16 0.18 tpc 16. conversion gain change vs. temperature, supply 3 v, ground reference mode, frequency 900 mhz temperature c 0.02 40 40 20 0 20 0.12 0.08 0.06 0.04 0.10 gain change v/v rms 0.00 0.02 0.04 60 80 100 mean 3 sigma 0.06 0.14 0.16 0.18 tpc 17. conversion gain change vs. temperature, supply 3 v, internal reference mode, frequency 900 mhz (micro_soic only) temperature c 0.02 40 40 20 0 20 0.12 0.08 0.06 0.04 0.10 gain change v/v rms 0.00 0.02 0.04 60 80 100 mean 3 sigma 0.06 0.14 0.16 0.18 tpc 18. conversion gain change vs. temperature, supply 3 v, supply reference mode, frequency 900 mhz (micro_soic only)
AD8361 rev. b C7C 67mv 370mv 270mv 25mv 5 s per horizontal division gate pulse for 900mhz rf tone rf input 500mv per vertical division tpc 19. output response to modulated pulse input for various rf input levels, supply 3 v, modulation frequency 900 mhz, no filter capacitor 67mv 370mv 25mv 500mv per vertical division 50 s per horizontal division rf input gate pulse for 900mhz rf tone 270mv tpc 20. output response to modulated pulse input for various rf input levels, supply 3 v, modulation frequency 900 mhz, 0.01 f filter capacitor AD8361 vpos iref rfin pwdn sref vrms fltr comm hpe3631a power supply c4 0.01 f c2 100pf hp8648b signal generator c1 0.1 f r1 75 c3 tek tds784c scope c5 100pf tek p6204 fet probe tpc 21. hardware con?guration for output response to modulated pulse input rf input 67mv 370mv 270mv 25mv 500mv per vertical division pwdn input 2 s per horizontal division tpc 22. output response using power-down mode for various rf input levels, supply 3 v, frequency 900 mhz, no filter capacitor 67mv 370mv 270mv 25mv 500mv per vertical division pwdn input 20 s per horizontal division rf input tpc 23. output response using power-down mode for various rf input levels, supply 3 v, frequency 900 mhz, 0.01 f filter capacitor AD8361 vpos iref rfin pwdn sref vrms fltr comm hpe3631a power supply c2 100pf hp8648b signal generator c1 0.1 f r1 75 c3 hp8110a pulse generator c4 0.01 f c5 100pf tek p6204 fet probe tek tds784c scope tpc 24. hardware con?guration for output response using power-down mode
AD8361 C8C rev. b carrier frequency mhz 7.8 7.6 6.2 100 1000 7.2 6.6 6.4 7.4 6.8 7.0 conversion gain v/v rms 6.0 5.8 5.6 v s = 3v tpc 25. c onversion gain change vs. freq uency, supply 3 v, ground reference mode, frequency 100 mhz to 2500 mhz, representative device 67mv 370mv 270mv 25mv 500mv per vertical division supply 20 s per horizontal division rf input tpc 26. output response to gating on power supply, for various rf input levels, supply 3 v, modulation frequency 900 mhz, 0.01 f filter capacitor AD8361 vpos iref rfin pwdn sref vrms fltr comm c2 100pf hp8648b signal generator c1 r1 75 hp8110a pulse generator 50 732 c4 0.01 f ad811 c5 100pf tek p6204 fet probe tek tds784c scope c3 0.1 f tpc 27. hardware con?guration for output response to power supply gating measurements conversion gain v/v rms 7.6 6.9 7.0 7.2 16 percent 7.4 7.8 14 12 10 8 6 4 2 0 tpc 28. conversion gain distribution frequency 100 mhz, supply 5 v, sample size 3000 iref mode intercept volts 0.40 0.32 0.34 0.36 percent 0.38 0.44 12 10 8 6 4 2 0 0.42 12 tpc 29. output reference, internal reference mode, supply 5 v, sample size 3000 (micro_soic only) sref mode intercept volts 0.72 0.64 0.66 0.68 percent 0.70 0.76 12 10 8 6 4 2 0 0.74 12 12 tpc 30. output reference, supply reference mode, supply 5 v, sample size 3000 (micro_soic only)
AD8361 rev. b C9C circuit description the AD8361 is an rms-responding (mean power) detector pro- viding an approach to the exact measurement of rf power that is basically independent of waveform. it achieves this function through the use of a proprietary technique in which the outputs of two identical squaring cells are balanced by the action of a high-gain error ampli?r. the signal to be measured is applied to the input of the ?st squaring cell, which presents a nominal (lf) resistance of 225 ? between the pin rfin and comm (connected to the ground plane). since the input pin is at a bias voltage of about 0.8 v above ground, a c oupling capacitor is required. by making this an external c omponent, the measurement range may be extended to arbitrarily low frequencies. the AD8361 responds to the voltage, v in , at its input, by squaring this v oltage to generate a current proportional to v in squared. this is applied to an internal load resistor, across which is con- nected a capacitor. these form a l ow-pass ?ter, which extracts the mean of v in squared. although essentially voltage-responding, the associated input im pedance cali brates t his port in terms of equivalent power. thus 1 mw corresponds to a voltage input of 447 mv rms. in the application section it is shown how to match this input to 50 ? . the voltage across the low-pass ?ter, whose frequency may be arbitrarily low, is applied to one input of an error-sensing ampli?r. a second identical voltage-squaring cell is used to close a negative feedback loop around this error amp li?r. this second cell is driven by a fraction of the quasi-dc ou tput voltage of the AD8361. when the voltage at the input of the second squaring cell is equal to the rms value of v in , the loop is in a stable state, and the output then represents the rms value of the input. the feedback ratio is nominally 0.133, making the rms-dc conversion gain 7.5, that is v out = 7.5 v in rms by completing the feedback path through a second squaring cell, identical to the one receiving the signal to be measured, several bene?s arise. first, scaling effects in these cells cancel; thus, the overall calibration may be accurate, even though the open-loop response of the squaring cells taken separately need not be. note that in implementing rms-dc conversion, no reference voltage enters into the closed-loop scal ing. second, the tracking in the responses of the dual cells remains very close over tem pera- ture, leading to excellent stability of calibration. the squaring cells have very wide bandwidth with an intrinsic response from dc to microwave. however, the dynamic range of such a system is fairly small, due in part to the much larger dynamic range at the output of the squaring cells. there are practical limitations to the accuracy with which very small error signals can be sensed at the bottom end of the dynamic range, arising from small random offsets; these set the limit to the attainable accuracy at small inputs. on the other hand, the squaring cells in the AD8361 have a ?lass-ab?aspect; the peak input is not limited by their quiescent bias condition, but is determined mainly by the eventual loss of square-law conformance. consequently, the top end of their response range occurs at a fairly large input level (about 700 mv rms) while preserving a reasonably accurate square-law response. the maximum usable range is, in practice, limited by the output swing. the rail-to-rail output stage can swing from a few millivolts above ground to less than 100 mv below the supply. an example of the output induced limit: given a gain of 7.5 and assuming a maximum output of 2.9 v with a 3 v supply; the maximum input is (2.9 v rms)/7.5 or 390 mv rms. filtering an important aspect of rms-dc con version is the need for averaging (the function is root-mean-square ). for complex rf waveforms such as occur in cdma, the ?tering provided by the on-chip low-pass ?ter, while satisfactory for cw signals above 100 mhz, will be inadequate when the signal has modulation components that extend down into the kilohertz region. for this reason, the fltr pin is provided: a capacitor attached between this pin and vpos can extend the averaging time to very low frequencies. offset an offset voltage can be added to the output (when using the micro_soic version) to allow the use of a/d converters whose range does not extend down to ground. however, accuracy at the low end will be degraded because of the inherent error in this added voltage. this requires that the pin i ref ( internal reference ) should be tied to vpos and sref ( supply reference ) to ground. in the iref mode, the intercept is generated by an internal reference cell, and is a ?ed 350 mv, independent of the supply voltage. to enable this intercept, iref should be open-ci rcuited, and sref should be grounded. in the sref mode, the voltage is provided by the supply. to implement this mode, tie iref to vpos and sref to vpos. the offset is then proportional to the supply voltage, and is 400 mv for a 3 v supply and 667 mv for a 5 v supply. using the AD8361 basic connections figures 2, 3, and 4 show the basic connections for the micro_soic version AD8361 in its three operating modes. in all modes, the device is pow ered by a single supply of between 2.7 v and 5.5 v. the vpos pin is decoupled using 100 pf and 0.01 f capacitors. the quiescent current of 1.1 ma in operating mode can be reduced to 1 a by pulling the pwdn pin up to vpos. a 75 ? external shunt resistance c ombines with the ac-coupled input to give an overall broadband i nput impedance near 50 ? . note that the coupling capacitor must be placed between the input and the shunt impedance. input impedance and input cou- pling are discussed in more detail below. the input coupling capacitor combines with the internal input resistance (figure 3) to give a high-pass corner frequency given by the equation f cr db cin 3 1 2 =
AD8361 C10C rev. b with the 100 pf capacitor shown in figures 2 4, the high- pass corner frequency is about 8 mhz. AD8361 vpos iref rfin pwdn sref vrms fltr comm 1 2 3 45 6 7 8 c c 100pf r1 75 cfltr 0.01 f 100pf +v s 2.7v 5.5v rfin v rms figure 2. ba sic connections for ground referenced mode AD8361 vpos iref rfin pwdn sref vrms fltr comm 1 2 3 45 6 7 8 c c 100pf r1 75 cfltr 0.01 f 100pf +v s 2.7v 5.5v rfin v rms figure 3. basic connections for internal reference mode AD8361 vpos iref rfin pwdn sref vrms fltr comm 1 2 3 45 6 7 8 c c 100pf r1 75 cfltr 0.01 f 100pf +v s 2.7v 5.5v rfin v rms figure 4. basic co nnections for supply referenced mode the output voltage is nominally 7.5 times the input rms voltage (a conversion gain of 7.5 v/v rms). three different modes of operation are set by the pins sref and iref. in addition to the ground referenced mode shown in figure 2, where the output voltage swings from around near ground to 4.9 v on a 5.0 v supply, two additional modes allow an offset voltage to be added to the output. in the internal reference mode, (figure 3), the output voltage swing is shifted upward by an internal reference voltage of 350 mv. in supply referenced mode (figure 4), an offset voltage of v s /7.5 is added to the output voltage. table i summarizes the connections, output transfer function and mini- mum output voltage (i.e., zero signal) for each mode. output swing figure 5 shows the output swing of the AD8361 for a 5 v supply voltage for each of the three modes. it is clear from figure 5, that operating the device in either internal reference mode or supply referenced mode, will reduce the effective dynamic range as the output headroom decreases. the respo nse for lower supply voltages is similar (in the supply referenced mode, the offset is smaller), but the dynamic range will be reduced further, as head- room d ecreases. figure 6 shows the response of the AD8361 to a cw input for various supply voltages. input v rms 5.0 4.5 0.0 0 0.5 0.1 0.2 0.3 0.4 3.0 1.5 1.0 0.5 4.0 3.5 2.0 2.5 output volts supply ref internal ref ground ref 0.6 0.7 0.8 figure 5. output swing for ground, internal and supply referenced mode. vpos = 5 v (micro_soic only) input v rms 5.5 1.5 0 0.5 0.1 0.2 0.3 0.4 4.0 3.0 2.5 2.0 5.0 4.5 3.5 output volts 1.0 0.5 0.0 5.5v 5.0v 3.0v 2.7v 0.6 0.7 0.8 figure 6. output swing for supply voltages of 2.7 v, 3.0 v, 5.0 v and 5.5 v (micro_soic only) dynamic range because the AD8361 is a linear responding device with a nomi- nal transfer function of 7.5 v/v rms, the dynamic range in db is not clear from plots such as figure 5. as the input level is in- creased in constant db steps, the output step size (per db) will also in crease. figure 7 shows the relationship between the out- put step size (i.e., mv/db) and input voltage for a nominal transfer function of 7.5 v/v rms. table i. connections and nominal transfer function for ground, internal, and supply reference modes output reference intercept mode iref sref (no signal) output ground vpos comm zero 7.5 v in internal open comm 0.350 v 7.5 v in + 0.350 v supply vpos vpos v s /7.5 7.5 v in + v s /7.5
AD8361 rev. b C11C input mv 700 200 0 500 100 200 300 400 500 400 300 600 mv/db 100 0 600 700 800 figure 7. idealized output step size as function of input voltage plots of output voltage vs. input voltage result in a straight li ne. it may sometimes be more useful to plot the error on a logarith- mic scale, as shown in figure 8. the deviation of the plot for the ideal straight line characteristic is caused by output clipping at the high end and by signal offsets at the low end. it should however be noted that offsets at the low end can be either posi- tive or negative, so that this plot could also trend upwards at the low end. tpcs 4, 5, 7, and 8 show a 3 sigma distribution of device error for a large population of devices. input v rms 2.0 0.5 0.01 0.5 0.0 1.5 1.0 error db 1.0 1.5 2.0 1.0 1.9ghz 2.5ghz 900mhz 100mhz 100mhz 0.02 ( 21dbm) 0.1 ( 7dbm) 0.4 (+5dbm) figure 8. representative unit, error in db vs. input level, v s = 2.7 v it is also apparent in figure 8 that the error plot tends to shift to the right with increasing frequency. because the input imped ance decreases with frequency, the voltage act ually applied to the input will also tend to decrease (assuming a constant source impedance over frequency). the dynamic range is almost con- stant over frequency, but w ith a small decrease in conversion gain at high frequency. input coupling and matching the input impedance of the AD8361 decreases with increasing frequency in both its resistive and capacitive components (tpc 12). the resistive component varies from 225 ? at 100 mhz down to about 95 ? at 2.5 ghz. a number of options exist for input matching. for operation at multiple frequencies, a 75 ? shunt to ground, as shown in f igure 9a, will provide the best overall match. for use at a single fre- quency, a resistive or a reactive match can be used. by plotting the input impedance on a sm ith chart, the best value for a resistive match can be calculated. the vswr can be held below 1.5 at frequencies up to 1 ghz, even as the input imped ance varies from part to part. (both input impedance and input c apaci- tance can vary by up to 20% around their nominal values.) at very high frequencies (i.e., 1.8 ghz to 2.5 ghz), a shunt re sis- tor will not be suf cient to reduce the vswr below 1.5. where vswr is critical, remove shunt component and insert an induc- tor in series with the coupling capacitor as shown in figure 9b. table ii gives recommended shunt resistor values for various frequencies and series inductor values for high frequencies. the coupling capacitor, c c , essentially acts as an ac-short and plays no intentional part in the matching. AD8361 rfin rfin r sh a. broadband resistor match AD8361 rfin rfin l m c c b. series inductor match AD8361 c c rfin rfin l m c m c. narrowband reactive match AD8361 c c rfin rfin r series d. attenuating the input signal figure 9. input coupling/matching options table ii. recommended component values for resistive or inductive input matching (figures 9a and 9b) frequency matching component 100 mhz 63.4 ? shunt 800 mhz 75 ? shunt 900 mhz 75 ? shunt 1800 mhz 150 ? shunt or 4.7 nh series 1900 mhz 150 ? shunt or 4.7 nh series 2500 mhz 150 ? shunt or 2.7 nh series
AD8361 C12C rev. b alternatively, a reactive match can be implemented using a shunt inductor to ground and a series capacitor as shown in figure 9c. a method for hand calculating the appropriate matching components is shown on page 12 of the ad8306 data sheet. matching in this manner results in very small values for c m , especially at high frequencies. as a result, a stray capacitance as small as 1 pf can signi cantly degrade the quality of the match. the main advantage of a reactive match is the increase in sensi- tivity that results from the input voltage be ing gained up (by the square root of the impedance ratio) by the matching network. table iii shows recommended values for reactive matching. table iii. recommended values for a reactive input match (figure 9c) frequency c m l m mhz pf nh 100 16 180 800 2 15 900 2 12 1800 1.5 4.7 1900 1.5 4.7 2500 1.5 3.3 input coupling using a series resistor figure 9d shows a technique for coupling the input s ignal into the AD8361, which may be applicable where the input signal is much larger than the input range of the AD8361. a se ries resistor combines with the input imp edance of the AD8361 to attenuate the input signal. since this series resistor forms a divider with the frequency-dependent input impedance, the apparent gain changes greatly with frequency. however, this method has the advantage of very little power being tapped off in rf power transmission applic ations. if the resistor is large compared to the transmission line s impedance then the vswr of the system is relatively unaffected. frequency mhz 200 0 500 resistance 100 0 250 150 50 1000 1500 2000 2500 3000 3500 0.2 0.5 0.8 1.1 1.4 1.7 capacitance pf figure 10. input impedance vs. frequency, supply 3v, sot-23-6l selecting the filter capacitor the AD8361 s internal 27 pf lter capacitor is connected in parallel with an internal resistance that varies with signal level from 2 k ? for small signals to 500 ? for large signals. the resulting low-pass corner frequency between 3 mhz and 12 mhz provides adequate ltering for all frequencies above 240 mhz (i.e., ten times the frequency at the output of the squarer, which is twice the input frequency). however, signals with high peak- to-average ratios, such as cdma or w-cdma signals, and with low frequency components, require additional ltering. tdma signals, such as gsm, pdc, or phs have a peak-to- average ratio that is close to that of a sinusoid, and the internal lter is adequate. the lter capacitance of the AD8361 can be augmented by connecting a capacitor between pin 6 (fltr) and vpos. table iv shows the effect of several cap acitor va lues for various communications standards with high peak-to-average ratios along with the residual ripple at the output, in peak-to-peak and rms volts. note that large lter capacitors will increase the enable and pulse response tim es, as discussed below. table iv. effect of waveform and c filt on residual ac output residual ac waveform c filt v dc mv p-p mv rms is95 reverse link open 0.5 550 100 1.0 1000 180 2.0 2000 360 0.01 f 0.5 40 6 1.0 160 20 2.0 430 60 0.1 f 0.5 20 3 1.0 40 6 2.0 110 18 is95 8-channel 0.01 f 0.5 290 40 forward link 1.0 975 150 2.0 2600 430 0.1 f 0.5 50 7 1.0 190 30 2.0 670 95 w-cdma 15 0.01 f 0.5 225 35 channel 1.0 940 135 2.0 2500 390 0.1 f 0.5 45 6 1.0 165 25 2.0 550 80 operation at low frequencies although the AD8361 is speci ed for operation up to 2.5 ghz, there is no lower limit on the operating frequency. it is only nec- essary to increase the input coupling capacitor to reduce the corner frequency of the input high-pass lter (use an input resis- tance of 225 ? for frequencies below 100 mhz). it is also necessary to incr ease the lter capacitor so that the signal at the output of the squaring circuit is free of ripple. the c orner fre- quency will be set by the combination of the in ternal resistance of 2 k ? and the external lter capacitance. power consumption, enable and power-on the quiescent current consumption of the AD8361 varies with the size of the input signal from about 1 ma for no signal up to 7 ma at an input level of 0.66 v rms (9.4 dbm re 50 ? ). if the input is driven beyond this point, the supply current increases steeply (see tpc 11). there is little variation in quiescent current with power supply voltage.
AD8361 rev. b C13C the AD8361 can be disabled either by pulling the pwdn (pin 4) to vpos or by simply turning off the power to the device. while turning off the device obviously eliminates the current consump- tion, disabling the device reduces the leakage current to less than 1 a. tpcs 22 and 23 show the response of the output of the AD8361 to a pulse on the pwdn pin, with no capacitance and with a lter capacitance of 0.01 f respectively; the turn-on time is a function of the lter capacitor. tpc 26 shows a plot of the output response to the supply being turned on (i.e., pwdn is grounded and vpos is pulsed) with a lter capacitor of 0.01 f again, the turn-on time is strongly influenced by the size of the lter capacitor. if the input of the AD8361 is driven while the device is disabled (pwdn = vpos), the leakage current of less than 1 a will increase as a function of input level. when the device is dis- abled, the output impedance increases to around 16 k ? . volts to dbm conversion in many of the plots, the horizontal axis is scaled in both rms volts and dbm. in all cases, dbm are calculated relative to an impedance of 50 ? . to convert between dbm and volts in a 50 ? . system, the following equations can be used. figure 10 shows this conversion in graphical form. power dbm v rms w v rms v rms w dbm dbm ( ) log () . log ( ( ) ) . log log / = ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = ? ? ? ? ? ? = ( ) 10 50 0 001 10 20 0 001 50 10 10 20 2 2 1 1 ? ? v rms dbm +20 +10 0 10 20 30 40 1 0.1 0.01 0.001 figure 11. conversion from dbm to rms volts output drive capability and buffering the AD8361 is capable of sourcing an output current of ap proxi- mately 3 ma. if additional current is required, a simple buffering circuit can be used as shown in figure 12c. similar circuits can be used to increase or decrease the nominal conversion gain of 7.5 v/v rms (figure 12a and 12b). in figure 12b, the ad8031 buffers a resistive divider to give a slope of 3.75 v/v rms. in figure 12a, the op amp s gain of two increases the slope to 15 v/v rms. using other resistor values, the slope can be changed to an arbitrary value. the ad8031 rail-to-rail op amp, used in these examples can swing from 50 mv to 4.95 v on a single 5 v supply and operate at supply voltages down to 2.7 v. if high output current is required (>10 ma), the ad8051, which also has rail- to-rail capability, can be used, down to a supply volt age of 3 v. it can deliver up to 45 ma of output current. 100pf 0.01 f AD8361 vout vpos comm pwdn 5k 5k 0.01 f 5v 15v/v rms ad8031 a. slope of 15 v/v rms AD8361 vout vpos comm pwdn 0.01 f 5v 3.75v/v rms ad8031 10k 5k 5k 100pf 0.01 f b. slope of 3.75 v/v rms 100pf AD8361 vout vpos comm pwdn 0.01 f 0.01 f 5v 7.5v/v rms ad8031 c. slope of 7.5 v/v rms figure 12. output buffering options
AD8361 C14C rev. b output reference temperature drift compensation the error due to low temperature drift of the AD8361 can be reduced if the temperature is known. many systems incorporate a temperature sensor; the output of the sensor is typically digi- tized, facilitating a software correction. using this information, only a two-point calibration at ambient is required. the output voltage of the AD8361 at ambient (25 c) can be expressed by the equation: v gain v v out in os = () + where gain is the conversion gain in v/v rms and v os is the extrapolated output voltage for an input level of 0 v. gain and v os (also referred to as intercept and output reference) can be calc ulated at ambient using a simple two-point calibration; that is, by measuring the output voltages for two specific input levels. calibration at roughly 35 mv rms ( 16 dbm) and 250 mv rms (+1 dbm) is recommended for maximum linear dynamic range. how ever, alternative levels and ranges can be chosen to suit the application. gain and v os are then cal culated using the equations: gain vv vv out out in in = ? () ? () 21 21 v v gain v os out in =? () 11 both gain and v os drift over temperature. however, the drift of v os has a bigger influence on the error relative to the output. this can be seen by inserting data from tpcs 13 and 16 (con- version gain and intercept drift) into the equation for v out . these plots are consistent with tpcs 9 and 10 which show that the error due to temperature drift decreases with increasing input level. this results from the offset error having a diminishing influence with increasing level on the overall measurement er ror. from tpc 13, the average intercept drift is 0.43 mv/ c from 40 c to +25 c and 0.17 mv/ c from +25 c to +85 c. for a less rigorous compensation scheme, the average drift over the complete temperature range can be calculated: drift v c vv cc vos / .. () = ?? () +?? () ? ? ? ? ? ? 0 010 0 028 85 40 = 0.000304 v/ c with the drift of v os included, the equation for v out becomes: v gain v v drift temp c out in os vos = () ++ ? () 25 the equation can be rewritten to yield a temperature compen- sated value for v in . v v v drift temp c gain in out os vos = ?? ? () () 25 figure 13 shows the output voltage and error (in db) as a func- tion of input level for a typical device (note that output voltage is plotted on a logarithmic scale). figure 14 shows the error in the calculated input level after the temperature compensation algorithm has been applied. for a supply voltage of 5 v, the part exhibits a worst case linearity error over temperature of approxi- mately 0.3 db over a dynamic range of 35 db. pin dbm 2.5 25 0 20 15 10 5 1.0 2.0 1.5 0.5 error db 510 +25 c 40 c 0 0.5 1.0 1.5 2.0 2.5 0.1 10 1.0 v out volts +85 c figure 13. typical output voltage and error vs. input level. 800 mhz, v pos = 5 v pin dbm 25 0 20 15 10 5 1.0 2.0 1.5 0.5 error db 510 0 0.5 1.0 1.5 2.0 2.5 +25 c 40 c +85 c 3.0 30 figure 14. error after temperature compensation of output reference. 800 mhz, v pos = 5 v
AD8361 rev. b C15C extended frequency characterization although the AD8361 was originally intended as a power mea- surement and control device for cellular wireless applications, the AD8361 has useful performance out to higher frequencies. typical applications may include mmds, lmds, wlan, and other noncellular activities. in order to recharacterize the AD8361 out to frequencies greater than 2.5 ghz, a small collection of devices were tested. dynamic range, conversion gain, and output intercept were measured at several frequencies over a temperature range of 30 c to +80 c. both cw and 64 qam modulated input wave forms were used in the characterization process in order to access varying peak-to-average waveform performance. the dynamic range of the device is calculated as the input power range over which the device remains within a permissible error margin to the ideal transfer function. devices were tested over frequency and temperature. after identifying an acceptable error margin for a given application, the usable dynamic measurement range can be identified using the plots in figures 15 through 18. for instance, for a 1 db error margin and a modulated carrier at 3 ghz, the usable dynamic range can be found by inspection of the 3 ghz plot of figure 18. note that the 30 c curve crosses the 1 db error limit at 17 dbm, for a 5 v supply the maximum input power should not exceed 6 dbm in order to avoid com- pression. the resultant usable dynamic range is therefore: 6 dbm ( 17 dbm ) or 23 dbm over a temperature range of 30 c to +80 c. pin dbm 2.5 25 error db 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 20 15 10 50 510 10 1 0.1 v out vo l t s +80 c +25 c 30 c figure 15. transfer function and error plots measured at 1.5 ghz for a 64 qam modulated signal pin dbm 2.5 25 error db 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 20 15 10 50 510 10 1 0.1 v out vo l t s +80 c +25 c 30 c figure 16. transfer function and error plots measured at 2.5 ghz for a 64 qam modulated signal pin dbm 2.5 25 error db 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 20 15 10 50 510 10 1 0.1 v out vo l t s +80 c +25 c 30 c figure 17. transfer function and error plots measured at 2.7 ghz for a 64 qam modulated signal pin dbm 2.5 25 error db 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 20 15 10 50 510 10 1 0.1 v out vo l t s +80 c +25 c 30 c figure 18. transfer function and error plots measured at 3.0 ghz for a 64 qam modulated signal
AD8361 C16C rev. b the transfer functions and error for a cw input and a 64 qam input waveform is shown in figure 19. the error curve is generated from a linear reference based on the cw data. the increased crest factor of the 64 qam modulation results in a decrease in output from the AD8361. this decrease in output is a result of the limited bandwidth and compression of the inter- nal gain stages. this inaccuracy should be accounted for in systems where varying crest factor signals need to be measured. pin dbm 2.5 25 error db 2.0 1.5 1.0 0.5 0 0.5 1.0 1.5 2.0 2.5 20 15 10 50 510 10 1 0.1 v out vo l t s cw 64 qam figure 19. error from cw linear reference vs. input drive level for cw and 64 qam modulated signals at 3.0 ghz frequency mhz 8.0 100 conversion gain v/v rms 7.5 7.0 6.5 6.0 5.5 5.0 200 400 800 1200 1600 2200 2500 2700 3000 figure 20. conversion gain vs. frequency for a typical device, supply 3 v, ground referenced mode the conversion gain is defined as the slope of the output voltage versus the input rms voltage. an ideal best fit curve can be found for the measured transfer function at a given supply volt- age and temperature. the slope of the ideal curve is identified as the conversion gain for a particular device. the conversion gain relates the measurement sensitivity of the AD8361 to the rms input voltage of the rf waveform. the conversion gain was measured for a number of devices over a temperature range of 30 c to +80 c. the conversion gain for a typical device is shown in figure 20. although the conversion gain tends to decrease with increasing frequency, the AD8361 does provide measurement capability at frequencies greater than 2.5 ghz. however, it is necessary to calibrate for a given application to accommodate for the change in conversion gain at a higher frequencies. dynamic range extension for the AD8361 the accurate measurement range of the AD8361 is limited by internal dc offsets for small input signals, and by square law conformance errors for large signals. the measurement range may be extended by using two devices operating at different sig- nal levels and then choosing only the output of the device, which provides accurate results at the prevailing input level. figure 21 depicts an implementation of this idea. in this circuit, the selection of the output is made gradually over an input level range of about 3 db in order to minimize the impact of imperfect matching of the transfer functions of the two AD8361s. such a mismatch typically arises because of the variation of the gain of the rf preamplifier u1 and both the gain and slope variations of the AD8361s with temperature. one of the AD8361s (u2) has a net gain of about 14 db preced- ing it and therefore operates most accurately at low input signal levels. this will be referred to as the weak signal path. u4, on the other hand, does not have the added gain and provides accurate response at high levels. the output of u2 is attenuated by r1 in order to cancel the effect of u2 s preceding gain so that the slope of the transfer function (as seen at the slider of r1) is the same as that of u4 by itself. the circuit comprising u3, u5, and u6 is a crossfader, in which the relative gains of the two inputs are determined by the output currents of a fuzzy comparator made from q1 and q2. assum- ing that the slider of r2 is at 2.5 v dc, the fuzzy comparator commands full weighting of the weak signal path when the out- put of u2 is below about 2.0 v dc, and full weighting of the strong signal path when the output of u3 exceeds about 3.0 v dc. u3 and u5 are otas (operational transconductance amplifiers).
AD8361 rev. b C17C u6 provides feedback to linearize the inherent tanh transfer function of the otas. when one ota or the other is fully selected, the feedback is very effective. the active ota will have zero differential input; the inactive one will have a poten- tially large differential input, but this does not matter because the inactive ota is not contributing to the output. however, when both otas are active to some extent, and the two signal inputs to the crossfader are different, it is impossible to have zero differential inputs on the otas. in this event, the crossfader admittedly generates distortion because of the nonlinear transfer function of the otas. fortunately, in this application, the dis- tortion is not very objectionable for two reasons: 1. the mismatch in input levels to the crossfader is never large enough to evoke very much distortion because the AD8361s are reasonably well-behaved. 2. the effect of the distortion in this case is merely to distort the otherwise nearly linear slope of the transition between the crossfader s two inputs. v out rf input level v rms transition region m 1 m 2 m 1 m 2 differing slopes indicate maladjustment of r1 figure 22. slope adjustment 8 7 6 5 1 2 3 4 AD8361 0.1 f 5v 100pf 5v 0.01 f 68 u2 era-3 20db u1 rfc 270 12v 6db pa d 6db splitter rf input 12v 20k 1k 1k 5v r2 10k q2 2n3906 q1 2n3906 16k r1 5k ca3080 +12v 5v u3 20k ca3080 +12v 5v u5 2 3 5 6 2 3 5 6 20k 1m r3 10k 5v +5v 12k 8 7 6 5 1 2 3 4 AD8361 0.1 f 5v 100pf 5v 0.01 f 68 u4 ad820 5v u6 2 3 8.2nf 4 7 6 v out 100 figure 21. range extender application this circuit has three trimpots. the suggested setup procedure is as follows: 1. preset r3 at midrange. 2. set r2 so that its slider s voltage is at the middle of the desired transition zone (about 2.5 v dc is recommended). 3. set r1 so that the transfer function s slopes are equal on both sides of the transition zone. this is perhaps best accom- plished by making a plot of the overall transfer function (using linear voltage scales for both axes) to assess the match in slope between one side of the transition region and the other. see figure 22. note: it may be helpful to adjust r3 to remove any large misalignment in the transfer function in order to correctly perceive slope differences. 4. finally (re)adjust r3 as required to remove any remaining misalignment in the transfer function (see figure 23). v out rf input level v rms transition region misalignment indicates maladjustment of r3 figure 23. intercept adjustment
AD8361 C18C rev. b in principle this method could be extended to three or more AD8361s in pursuit of even more measurement range. how- ever, it is very important to pay close attention to the matter of not excessively overdriving the AD8361s in the weaker signal paths under strong signal conditions. figure 24 shows the extended range transfer function at mul- tiple temperatures. the discontinuity at approximately 0.2 v rms arises as a result of component temperature dependencies. fig- ure 25 shows the error in db of the range extender circuit at ambient temperature. for a 1 db error margin the range extender circuit offers 38 db of measurement range. drive level v rms 3.0 2.5 0 0 1.0 0.2 v out v 0.4 0.6 0.8 2.0 1.5 1.0 0.5 ref line +80 c 30 c figure 24. output vs. drive level over temperature for a 1 ghz 64 qam modulated signal drive level dbm 5 32 error db 4 3 2 1 0 1 2 3 4 5 27 22 17 12 7 23 813 13 figure 25. error from linear reference at 25 c for a 1 ghz 64 qam modulated signal evaluation board figures 26 and 29 show the schematic of the AD8361 evalua- tion board. note that uninstalled components are drawn in as dashed. the layout and silkscreen of the component side are shown in figures 27, 28, 30, and 31. the board is powered by a single supply in the range, 2.7 v to 5.5 v. the power supply is decoupled by 100 pf and 0.01 f capacitors. additional decoupling, in the form of a series resistor or inductor in r6, can also be added. table v details the various con guration options of the evaluation board. table v. evaluation board con?uration options component function default condition tp1, tp2 ground and supply vector pins. not applicable sw1 device enable. when in position a, the pwdn pin is connected to +v s and sw1 = b the AD8361 is in power-down mode. in position b, the pwdn pin is grounded, putting the device in operating mode. sw2/sw3 operating mode. selects either ground referenced mode, internal reference sw2 = a, sw3 = b mode or supply reference mode. see table i for more details. (ground reference mode) c1, r2 input coupling. the 75 ? resistor in position r2 combines with the AD8361 s r2 = 75 ? (size 0402) internal input impedance to give a broadband input impedance of around 50 ? . c1 = 100 pf (size 0402) for more precise matching at a particular frequency, r2 can be replaced by a different value (see input matching and figure 9). capacitor c1 ac-couples the input signal and creates a high-pass input lter whose corner frequency is equal to approximately 8 mhz. c1 can be increased for operation at lower frequencies. if resistive attenuation is desired at the input, series resistor r1, which is nominally 0 ? , can be replaced by an appropriate value. c2, c3, r6 power supply decoupling. the nominal supply decoupling of 0.01 f and c2 = 0.01 f (size 0402) 100 pf. a series inductor or small resistor can be placed in r6 for additional c3 = 100 pf (size 0402) decoupling. r6 = 0 ? (size 0402) c5 filter capacitor. the internal 50 pf averaging capacitor can be augmented c5 = 1 nf (size 0603) by placing a capacitance in c5. c4, r5 output loading. resistors and capacitors can be placed in c4 and r5 to c4 = r5 = open load test v rms. (size 0603)
AD8361 rev. b C19C AD8361 vpos iref rfin pwdn sref vrms fltr comm c1 100pf r2 75 c5 1 2 3 45 6 7 8 c2 0.01 f rfin v rms c3 100pf vpos v s sw2 v s sw3 sw1 a b a b r5 (open ) r4 0 1nf c4 (open ) r6 0 a b tp2 tp1 vpos vpos figure 26. evaluation board schematic micro_soic figure 27. layout of component side micro_soic figure 28. silkscreen of component side micro_soic c5 1nf c3 100pf c2 0.01 f j2 j3 j1 r2 75 tp2 r4 0 c4 open r5 open AD8361 vpos rfin pwdn vrms fltr comm 1 2 3 4 5 6 tp1 c1 100pf sw1 1 2 3 r7 50 vpos "
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C20C c01088aC2C2/01 (rev. b) printed in u.s.a. AD8361 rev. b problems caused by impedance mismatch may arise using the evaluation board to examine the AD8361 performance. one way to reduce these problems is to put a coaxial 3 db attenuator on the rfin sma connector. mismatches at the source, cable, and cable interconnection, as well as those occurring on the evaluation board can cause these problems. a simple (and common) example of such problem is triple travel due to mismatch at both the source and the evaluation board. here the signal from the source reaches the evaluation board and mismatch causes a reflection. when that reflection reaches the source mis match, it causes a new reflection, which travels back to the evaluation board adding to the original signal inci- dent at the board. the resultant voltage will vary with both cable length and frequency dependent upon the relative phase of the initial and reflected signals. placing the 3 db pad at the input of the board improves the match at the board and thus reduces the sensitivity to mismatches at the source. when such precautions are taken, measurements will be less sensitive to cable length and other fixturing issues. in an actual application when the distance between AD8361 and source is short and well defined, this 3 db attenuator is not needed. characterization setups equipment the primary characterization setup is shown in figure 33. the signal source used was a rohde & schwarz smiq03b, version 3.90hx. the modulated waveforms used for is95 reverse link, is95 nine active channels forward (forward link 18 setting), w-cdma 4- and 15-channel were generated using the default settings coding and ltering. signal levels were calibrated into a 50 ? impedance. analysis the conversion gain and output reference are derived using the coef cients of a linear regression performed on data collected in its central operating range (35 mv rms to 250 mv rms). this range was chosen to avoid areas of operation where offset distorts the linear response. error is stated in two forms error from linear response to cw waveform and output delta from 25 c performance . the error from linear response to cw waveform is the difference in output from the ideal output de ned by the conversion gain and output reference. this is a measure of both the linearity of the device response to both cw and modulated waveforms. the error in db uses the conversion gain multiplied times the input as its reference. error from linear response to cw waveform is not a measure of absolute accuracy, since it is calculated using the gain and output reference of each device. but it does show the linearity and effect of modulation on the device response. error from 25 c performance uses the performance of a given device and waveform type as the reference; it is predomi- nantly a measure of output variation with temperature. AD8361 vpos iref rfin pwdn sref vrms fltr comm c1 0.1 f r1 75 1 2 3 45 6 7 8 rfin c3 c4 0.1 f c2 100pf iref pwdn vpos sref vrms figure 32. characterization board AD8361 characterization board rfin prup +v s sref iref vrms dc output rf signal smiq038b rf source ieee bus pc controller dc matrix / dc supplies / dmm dc sources 3db attenuator "
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, ' 8-lead mi cro_soic package (rm-8) 0.009 (0.23) 0.005 (0.13) 0.028 (0.70) 0.016 (0.40) 6 0 0.037 (0.95) 0.030 (0.75) 85 4 1 0.122 (3.10) 0.114 (2.90) pin 1 0.0256 (0.65) bsc 0.122 (3.10) 0.114 (2.90) 0.193 (4.90) bsc seating plane 0.006 (0.15) 0.002 (0.05) 0.016 (0.40) 0.010 (0.25) 0.043 (1.10) max outline dimensions dimensions shown in inches and (mm). 6-lead sot-23-6l package (rt-6) 0.122 (3.10) 0.106 (2.70) pin 1 0.118 (3.00) 0.098 (2.50) 0.075 (1.90) bsc 0.037 (0.95) bsc 1 3 4 5 6 2 0.071 (1.80) 0.059 (1.50) 0.009 (0.23) 0.003 (0.08) 0.022 (0.55) 0.014 (0.35) 10 0 0.020 (0.50) 0.010 (0.25) 0.006 (0.15) 0.000 (0.00) 0.051 (1.30) 0.035 (0.90) seating plane 0.057 (1.45) 0.035 (0.90)

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